Senior Digital Simulator EDA Software Engineer / Architect

компания "ventra" since its establishment in 2010, primarius’s founding team has been guided by the concept of "design for yield (dfy) to enhance the competitiveness of ic design and manufacturing" to conduct forward-looking technology research and development and product layout, carry out eda process innovation. we have offices in asia and usa and now are opening the office in russia. we search for young and high professionals located in different cities in russia to join our friendly international team. we’re looking for senior position in our digital simulation team for following areas: high-performance hdl simulation core algorithm development for rtl and gate level functional verification verilog parallel simulation algorithm development and gpu hardware acceleration verilog/systemverilog/verilogams/vhdl/systemc compilation optimization job responsibilities: design and implementation key algorithm for hdl simulation product digital simulation enhancement on performance, capacity and features. lead team for product development, testing and release (for leader or architect) key qualifications: phd or ms in computer science or electrical engineering, a minimum of 2 years of relevant experience strong capability in c++ programming strong verbal and written communication skills ability to work productively in a team environment familiar with hdl simulation technology and ic verification flow familiar with systemverilog/verilog/vhdl/systemc language and testbench experience in digital ic design & verification would be a plus fluent spoken and written english working conditions: competitive salary remote work or office+remote in st. petersburg/moscow medical insurance compensation of meals and phone/internet expenses