Senior Digital Simulator EDA Software Engineer and Architect

Since its establishment in 2010, Primarius’s founding team has been guided by the concept of "Design for Yield (DFY) to enhance the competitiveness of IC design and manufacturing" to conduct forward-looking technology research and development and product layout, carry out EDA process innovation. Primarius have offices in Asia and USA and now are opening the office in Russia. We’re looking for Senior position in our digital simulation team for following areas: High-performance HDL simulation core algorithm development for RTL and gate level functional verification; Verilog parallel simulation algorithm development and GPU hardware acceleration; Verilog/SystemVerilog/VerilogAMS/VHDL/SystemC compilation optimization. Responsibilities: Design and implementation key algorithm for HDL simulation product; Digital simulation enhancement on performance, capacity and features; Lead team for product development, testing and release (for leader or architect). Requirements: Demonstrated strong capability in C++ programming; Strong verbal and written communication skills; Ability to work productively in a team environment; Familiar with HDL simulation technology and IC verification flow; Familiar with SystemVerilog/Verilog/VHDL/SystemC language and testbench; PhD or MS in Computer Science or Electrical Engineering, a minimum of 2 years of relevant experience; Experience in digital IC design & verification would be a plus. Conditions: Competitive salary; Remote work or office+remote in St. Petersburg/Moscow; Medical insurance; Compensation of meals and phone/internet expenses.