About Us At RapidSilicon, we focus on bringing creativity to FPGA design by combining open-source FPGA methodology with proprietary technologies that enable a faster design-to-silicon turnaround. Our employees work on innovative AI-enhanced EDA tools to provide the most optimized design result that satisfies the needs in general-purpose or domain-specific applications. To view our job listings, please visit our Careers page. Job Description In this role you will be required to define, implement, and verify DFT architecture and features for Scan / MBIST / JTAG / ATPG / boundary-scan for our next generation FPGA product. Take lead to setup DFT development methodologies, plans, and schedules, on top of performing ATPG patterns verification with gate-level simulation. You will be at the fore-front in deciding the tradeoff of test coverage and test cost, while supporting post-silicon bring-up and yield analysis. Minimum Qualifications Master with at least 6 years or Bachelor with at least 8 years demonstrated experience in DFT for VLSI designs. Expert in scan insertion, ATPG, MBIST, JTAG, boundary scan, Scan Compression, and at-speed testing. Excellent debugging skills for RTL and gate-level simulations. Knowledge of defect types, fault models, debugging, and validation on ATE and silicon bring-up. Preferred Skills Proven leadership skills. Good communication skills and the ability to work with teams crossing different geos. Prior experience in engaging Design teams on pre-Silicon test planning and validation.
Адрес
Санкт-Петербург